1. Field of the Invention
The present invention relates to a semiconductor device, and, more particularly, to a method for fabricating a porous Low-k film of multi-layered wiring.
2. Description of Related Art
In recent years, in accordance with the demand to lower the power consumption and increase the speed of semiconductor devices, a need has arisen to lower the permittivity of interlayer insulating films. Particularly in the case of logic-based devices, the increased resistance caused by fine wiring and the increase in the wiring capacitance have been linked to degradation of the speed of the device, and hence there is now a need for fine multi-layered wiring whose interlayer insulating film is a low permittivity film. Currently, the most widely used interlayer insulating film in semiconductor devices is a silicon oxide film formed by Chemical Vapor Deposition (CVD) the relative permittivity value of this film being on the order of 4. SiOF, which contains fluorine atoms (relative permittivity=3.2 to 3.7 approximately), is well known as a low permittivity film that is deposited by using CVD. By terminating the Si—O—Si bond with an F atom, the permittivity of the material is reduced because of the reduced density thereof and the fact that the polarizability of the F atoms themselves is low, and so forth. Furthermore, organic SOG (SOG: Spin on Glass) and polyimide and so forth are well known as low dielectric materials that contain carbon atoms. Organic SOG is also referred to as silica-based organic coating film, and representative material examples include MSQ (methyl silsesquioxane) and HSG, and so forth. The density of these materials is reduced by the inclusion of carbon atoms, so-called alkyl groups, and it is said that low permittivity results from reducing the polarizability of the molecules themselves. The relative permittivity of these films is on the order of 2.5 to 3.5. The film deposition method generally used is a technique that involves coating the substrate uniformly by coating the substrate with an organic solution and then rotating the substrate at a high speed by using a spin coater, and finally drying (sintering) the solution by annealing the substrate at a temperature of 120° C. to 300° C.
Meanwhile, a method that reduces the permittivity by lowering the density has also been investigated. That is, this method involves lowering the density per unit volume to reduce the permittivity by including voids or air holes (bubbles) in a silicon oxide film or other film. Because the relative permittivity of the voids is 1, implementation is possible up to a relative permittivity that is on the order of 1.5 by increasing the void content. The void content here is on the order of 50% to 60%, varying according to the organic silica-based film type. Such a low permittivity insulating film that contains voids in the film is called a porous Low-k film. The voids are formed by adding a foaming agent as a porosity agent to the material, vaporizing the foaming agent by carrying out a heat treatment step such as curing, followed by decomposition. An organic silicon compound is generally used as the foaming agent. Foaming agents may also be in granular form, and there are also techniques such as that of diffusing a granular foaming agent in a film deposition material, coating this film deposition material on the substrate and then subjecting the same to a heat treatment to form voids in the film. Silica powder with a grain diameter of 1 to 50 nm or 5 to 15 nm is used as the granular foaming agent.
Furthermore, as an example in which a porous Low-k film is used as an interlayer insulating film, a method in which only a portion in the vicinity of a side wall face exposed to a wiring groove and via hole connecting hole of the interlayer insulating film is a porous Low-k film has also been proposed (Japanese Patent Application Laid Open No. 2002-231808 (paragraphs 0039 to 0043, FIG. 2), corresponding to U.S. Patent Application Publication No. US2002/0105086A1).
Here, a method for forming a multi-layered wiring film in which a general porous Low-k film is used as the interlayer insulating film will be described. FIGS. 9 and 10 are explanatory views of a process for fabricating multi-layered wiring in which a conventional porous Low-k film is used as the insulating film.
First of all, an etching stopper layer 202 for forming a wiring groove 210 is deposited on lower layer wiring 200. Here, as an example of the etching stopper layer, a silicon nitride film (Si3N4) 202 is employed. Then, a porous Low-k film 204 is deposited as an interlayer insulating film for forming the wiring groove 210 therethrough. Next, a silicon oxide film 206 constituting a hard mask is deposited (FIG. 9(A)). Next, patterning of a resist pattern 208 used for the wiring groove is performed by using a photolithographic technique (FIG. 9(B)). The inside of the wiring groove 210 is formed by etching the silicon oxide film 206 and the porous Low-k film 204, and the resist pattern 208 is then removed (FIG. 9(C)). The wiring groove 210 is chemically cleaned to remove impurities. Next, a barrier metal 212, a seed layer (not shown), and an electrically conductive layer 214 are formed in this order. Then excess metal is removed by polishing by means of Chemical Mechanical Polishing (CMP), thereby forming wiring 215 (FIG. 10(A)). Finally, a silicon nitride film 216 is deposited as a metal wiring cap film (FIG. 10(B)). The silicon nitride film 216 also functions as an etching stopper film for an upper wiring layer. Multi-layered wiring that uses a porous Low-k film is formed by repeating the steps described above.
However, the following three problems manifest themselves when an insulating film containing voids is applied to multi-layered wiring.
First, “1) Film quality degradation resulting from plasma irradiation during etching and ashing” may be cited as the very first problem. This problem is based on the fact that, generally, organic films such as the organic SOG mentioned above possess the property of being susceptible to a heat treatment in a plasma oxide atmosphere, thereby producing a variation in film quality (conversion to SiO2 through compaction) during plasma oxide ashing to process the via hole and remove the resist and so forth. It is thought that this phenomenon is generated as a result of the oxygen radical (O*) in the plasma penetrating the film via the pattern side wall of the organic SOG film during ashing and then reacting with the alkyl groups within the film (methyl groups or similar). Hence there is the worry that, when the organic SOG film surface is processed directly by the oxygen-containing plasma in an etching and ashing step, the SOG film surface will modify the oxygen film and the permittivity will increase due to moisture absorption.
Next, “2) The penetration of chemical into the voids during cleaning” may be mentioned. This induces problems such as a short circuit between the wiring or interconnection as a result of the chemicals during the cleaning following the etching penetrating the interlayer insulating film via these voids on account of the exposure of the voids at the pattern side walls in the cleaning step following etching. This brings about the concern that the reliability and yield of the device will be affected as a result.
Further, the “3) Reduction in the coverage of the barrier metal caused by the voids” may be mentioned. Because the material containing voids in the film is etched, when contacts or similar are formed, it is to be expected that the surface of the pattern side wall will exhibit severe side wall unevenness that is caused by these voids. At these rough points of the pattern side wall, the coverage (surface coverage) of the film that is deposited subsequently is markedly reduced, and, therefore, when a film with an extremely thin film thickness is deposited as a barrier metal (20 to 50 nm), for example, points exist, depending on the location, in which the barrier metal is not formed. There is therefore the concern that, when a point that is partially uncovered by the barrier metal exists, copper or the like will be diffused within the insulating film as a result of a subsequent heat treatment or similar, thereby inducing a short circuit with the adjoining wiring or degradation of the device characteristics and so forth, and reducing the yield.
As a method for avoiding the above-described problems which are generated during formation of the above-described wiring layer, a method that involves forming a wiring groove and via hole connecting hole and then protecting the side walls of the porous Low-k film by means of a side wall has been proposed (Japanese Patent Application Laid-Open No. 10-284600 (paragraphs 0025 to 0032, FIG. 3)). Further, as another technique, a method that involves modifying the end surfaces of the insulating film by means of compaction has also been proposed (Japanese Patent Application Laid-Open No. 2001-77086 (paragraphs 0004 to 0005, FIG. 1), corresponding to U.S. Pat. No. 6,355,572).
However, both these techniques are techniques that cover the voids by forming a side wall or modified film and so forth, and hence there is the concern that, when points that are partially unprotected or unmodified exist, the porous Low-k film will be damaged.
Accordingly, there has been a desire for a method of overcoming the three problems mentioned above and of forming a multi-layered wiring film in which there is no damage to the porous Low-k film.